Execute synthesis, place-and-route and STA for ASIC partitions from RTL to silicon. Collaborate with architects, RTL designers and DFT engineers to close EM/IR, LEC and physical verification signoff. Improve physical design methodologies (synthesis, PnR, EMIR, PDN), troubleshoot flows and work with EDA vendors to resolve issues while meeting tight schedules and low-power goals.

Lead full-chip DFT architecture and implementation including scan, compression, MBIST/BIST, ATPG vector generation, gate-level verification, and silicon debug. Collaborate with STA, physical design, memory compiler, and test teams to ensure production-ready silicon with high test coverage and diagnostic capability, and support bring-up and debug on silicon.