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The Digital Design Engineer will design and optimize DSP algorithms for high-speed SERDES, collaborating with cross-functional teams to integrate solutions into advanced systems.

Drive the design and integration of SoCs focusing on high-speed interconnects and ASIC execution, optimizing RTL for power and performance. Collaborate with teams for verification and post-silicon validation.

The role involves developing high-performance digital designs for ASICs, optimizing power, performance, and area while ensuring timing closure and conducting post-silicon validation.

The Principal Design Engineer will lead SoC design and integration, focusing on high-performance components and RTL design, collaborating across teams to optimize power, performance, and area.