The role involves defining Mixed-Signal IP requirements, managing integration processes, supporting debug for analog circuits, and designing CMOS integrated circuits.

Design, simulate, and validate analog and mixed-signal IC blocks for SoCs, including PLLs, ADCs/DACs, high-speed I/Os and MEMS drivers. Develop behavioral models for mixed-signal simulations and perform block-level silicon validation and system-level lab evaluation.

Lead architecture and transistor-level design of high-performance analog/mixed-signal IP (PLLs, ADC/DAC, filters, high-speed I/O). Provide technical leadership, mentor designers, develop behavioral/Verilog-A models, drive Cadence-based flows, and support silicon bring-up, validation, characterization, and cross-functional integration for SoC environments.