Perform RTL-to-physical-design activities including RTL synthesis, SDC constraint creation and validation, static timing analysis, synthesis and STA debugging, and clean netlist generation. Develop or modify synthesis, constraint, and timing-analysis scripts. Work with EDA tools including Design Compiler, PrimeTime, Tempus, and Genus across advanced semiconductor process nodes such as 16nm and 7nm.

Perform RTL-to-physical-design activities, including RTL synthesis, constraint and SDC writing, validation, static timing analysis, scripting, synthesis and STA debugging, and clean netlist generation. The role requires hands-on experience with Design Compiler, PrimeTime, Tempus, and Genus, plus multi-node ASIC design experience across technologies such as 16nm and 7nm.