Perform RTL-to-physical-design activities including RTL synthesis, SDC constraint creation and validation, static timing analysis, synthesis and STA debugging, and clean netlist generation. Develop or modify synthesis, constraint, and timing-analysis scripts. Work with EDA tools including Design Compiler, PrimeTime, Tempus, and Genus across advanced semiconductor process nodes such as 16nm and 7nm.
Need Design Engineer with very strong experience Timing Constraints Writing.
RTL to Physical Design (RTL2PD) stage experience
RTL2PD Design Engineer(ASIC)
MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis
What candidate will Be Doing:
RTL Synthesis, Constraint writing, validation, Static timing Analysis
Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
Debug synthesis issues and STA
Generate clean netlist.
What we are looking for:
Experience: 8–12 years of hands-on RTL Synthesis
EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
Multi-Node Design: Experience working with 16nm, 7nm… etc nodes
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