Leads end-to-end technical programs across multiple engineering teams, managing roadmaps, schedules, milestones, risks, dependencies, resources, and stakeholder communication. Drives alignment among engineering, product, quality, and operations teams while reporting progress to leadership and improving program management processes. The role requires 5–10 years of technical program management experience, an engineering degree, and strong cross-functional leadership skills.

Designs next-generation PCIe Gen6/Gen7 switch ASIC IP from architecture and micro-architecture through RTL implementation, verification support, emulation, and tape-out. Responsibilities include developing synthesizable SystemVerilog, optimizing high-performance pipelines, supporting timing and design closure, debugging silicon and protocol issues, collaborating with verification teams, and mentoring engineers. The role requires strong ASIC/SoC logic design expertise, PCIe knowledge, EDA tool experience, and technical leadership.