Teams at Intel

Lead and execute post-silicon functional validation for SerDes IP: develop validation strategies, design test plans and infrastructure, debug mixed-signal issues, perform root-cause analysis, document results, and collaborate with architecture, design, board, platform, and manufacturing teams to optimize validation and failure resolution.

Design and execute mixed-signal presilicon verification plans, build testbenches and behavioral models, debug and root-cause presilicon issues, collaborate with digital/analog architects and RTL/physical design teams, and improve verification infrastructure using scripting and AI-based tools.

The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.